Linear mode definition

During linear mode a MOSFET operates in its saturated state, or saturation region, and it behaves as a (gate) voltage controlled current source. Contrary to what happens when fully ON (or fully enhanced), the drain-source impedance is relatively high, resulting in high power dissipation. In linear mode, the power is given by the product of the drain current and the drain-source voltage (I_D × V_DS), which are both high at the same time.

Linear mode can be described analytically by the set of equations below. The MOSFET needs to be ON (Equation 1) and the V_DS greater than the overdrive voltage (V_OD) (Equation 2). If the previous two conditions are met the drain current will be proportional to the square of V_OD (thus the applied V_GS) as shown in Equation 3, where k is a technological parameter fixed with the type of trench technology used.

(Eq. 1)  

(Eq. 2)  

(Eq. 3)  

Temperature dependency

Thermal instability

For a fixed V_DS, the variation of drain current against gate bias voltage is plotted in the transfer characteristic graph, shown in Fig. 4. Two lines are used to show the MOSFET operation at a junction temperature of 25 °C (solid line) and 175 °C (dashed line). For a low enough V_GS, the MOSFET will conduct more current if it operates at 175 °C than at 25 °C, due to the negative temperature coefficient of the threshold voltage (V_GSth), as shown in Fig. 5. In this case the MOSFET is operating in a region of thermal instability, identified by a positive temperature coefficient of the current. This holds true even when considering a single spot on the silicon die ^[1].

However, this phenomenon can be avoided. In fact, for a given V_DS, there is a critical current above which there is a negative feedback and thus thermal stability. This is known as the Zero Temperature Coefficient (ZTC) point.

On the SOA graph, thermal instability is indicated by a two-slopes line and an additional inflexion point, as shown in Fig. 6 (the inflexion point is located at 5 V for a 1 ms pulse). The theoretical limit, in the dashed blue line, is calculated using Equation 4, where Z_th = Z_th(j-mb). This limit can be found using an RC thermal model, like the Cauer model shown in Fig. 7. The dashed red line indicates the real performance of the device. In this case Z_th ≠ Z_th(j-mb) and therefore the limit cannot be found using an electrical model. The reduction in performance can be quite severe: in this case for a V_DS of 20 V, the maximum current the MOSFET can handle goes from a theoretical 60 A down to around 15 A (75% less). This phenomenon is also known as Spirito effect, and it is  caused by the uneven distribution of current across the silicon die. Below the ZTC point, if a small region is at a higher temperature than the rest of the die, it will draw more current and dissipate more power becoming even hotter. This process eventually leads to thermal runaway and the destruction of the MOSFET as a three-terminal short. Burn marks will appear near the center of the die and close to the die bonding structure, as documented in AN11243 Failure signature of electrical overstress on power MOSFETs (1.3 Linear mode operation).

Moreover, these hotspots are observed to occur more frequently at wider power pulses.

With reference to Fig. 6, for a time pulse of 10 ms the Spirito effect takes place at a lower V_DS (around 3 V) than for the 1 ms pulse (5 V) while DC operation is limited by thermal instability at any voltage.

The uneven distribution of current across the silicon die is influenced by uniformity of the MOSFET cells and integrity and uniformity of the die attachment. Besides, the type of die bonding technology can also have a significant impact. As shown in Fig. 8, wire bonding increases current density in small points of the die that can become hot spots. On the other hand, the copper clip of an LFPAK prevents localised current crowding reducing the likelihood of hot spot formation.

Also, cell density influences the shape of the SOA. Older trench (or planar) technologies show a higher R_DSon, due to the wider cell pitch and thus lower cell density. For a given total drain current, cells in older technologies are more likely to operate beyond the ZTC point, where operation is thermally stable, since the current per cell is higher. Consequently, for a given die size, older trench (or planar) technologies show a higher R_DSon but in turn perform better in linear mode.
The innovation introduced with new trench structures has deeply increased performances in some of the other fields, particularly in switching, avalanche and steady state behavior. Newer technologies show generally worse linear mode capability, however, whenever harder requirements have to be met the designer can either choose (in case the thermal design cannot be improved): a MOSFET with a lower R_th(j-mb) (corresponding to a bigger die), a bigger package, an older technology (with lower cell density) or a MOSFET from Nexperia’s ASFET portfolio with Enhanced SOA capability.

Table 1 summarizes the current limits predicted using the three methods and measurement at V_DS = 30 V, T_mb = 125 °C and pulse of 1 ms.

Before applying any of these methods, the power scale factor (k_PSF) must be calculated. This can be obtained by looking at the plot in Fig. 10, or using Equation 5. The graph is given in any Nexperia’s data sheet and represents the normalized power dissipation as a function of mounting base temperature. Due to its double scaling, the power scaling method make use of a different coefficient calculated using Equation 6.

(Eq. 5) 

(Eq. 6)  

As an example, a MOSFET’s current limit is calculated using the current scaling method for: T_mb = 100 °C, V_DS = 3 V and a pulse width of 1 ms

1. The current limit at T_mb = 25 °C is 400 A, as shown in Fig. 11
2. k_PSF is calculated using Equation 5 and is exactly 0.5 (i.e. 50%)
3. The new limit at T_mb = 100°C is 200 A, as calculated using Equation 7. 

(Eq. 7)  

The complete Hot-SOA graph can be found by taking the following steps (current scaling method is used but this can be adapted to the other methods):

• The R_DSon limit is not derated since it is calculated using R_DSon at 175 °C
• Linear mode inflexion point and breakdown limit are shifted downwards, the new current limits are found using the power scale factor (in this case 0.5). A new inflexion point for the Spirito region is generated at half the current of the original one
• Finally, the lines can be extended to the endpoints using the same slope.

SOA: pulse shape conversion

In certain applications the power may not be a rectangular pulse, or the duration may be different from the set given in the SOA graph. In both cases a power shape conversion can be carried out and operation within SOA verified. This conversion is exact if the MOSFET is operating in ohmic mode or linear mode. However, it might be inaccurate for operation in the Spirito region.

If the MOSFET is not working in Spirito region, the pulse can be converted into a rectangular one carrying the same amount of energy, by adjusting either the duration or the peak. Fig. 13 shows the conversion for a triangular power pulse. If the pulse duration is not part of the SOA graph, the limit can be calculated using the value of thermal impedance found in the data sheet (or an RC thermal model) and Equation 4. The use of thermal and electrothermal models is always recommended to accurately predict the junction temperature.

Active clamping is used in inductive switching, similarly to avalanche, however the device operates in linear mode at a lower clamping voltage than in avalanche. With switch sw1 on the closed position and MOSFET M1 turned ON, current can flow through the main circuit. Once the inductor is “charged” the MOSFET is switched OFF. The energy stored in the inductor induces a high voltage that breaks down the Zener diode ZD1. This, in turn, clamps the gate voltage turning ON the MOSFET, which absorbs the energy released by the inductor. During this last activation the MOSFET is working in linear mode, the V_DS is fairly constant while its drain current decreases, as shown in Fig. 14 (simulated). Therefore, the dissipated power is a triangular pulse lasting 1 ms.

The circuit is used to test the BUK7S1R0-40H at V_DS of 20 V, 22 V and 28 V. The limit is obtained by derating the current at which destruction occurs by applying the same methodology used for the SOA in data sheets. Fig. 15 shows the current capability against time in avalanche (I_AL) and during active clamp at different clamping voltages. Table 2 summarises the results from the graph at a pulse of 1 ms. The current capability for a triangular pulse is shown to be around 2x the one for a rectangular pulse. The current decreases as the voltage increases, as expected in case of rectangular pulses.