74CBTLV3306
2-bit bus switch
The 74CBTLV3306 is a 2-bit high-speed bus switch with separate output enable inputs (nOE). Each switch is disabled when the associated output enable (nOE) input is HIGH.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current?-?sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Features and benefits
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
4 Ω switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD78B Class I level A
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | VPASS (V) | Logic switching levels | RON (Ω) | f(-3dB) (MHz) | Nr of bits | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74CBTLV3306DC | 2.3?-?3.6 | 5 | CMOS/LVTTL | 7 | 400 | 2 | 0.2 | very low | -40~125 | 202 | 33.5 | 112 | VSSOP8 |
| 74CBTLV3306GT | 2.3?-?3.6 | 5 | CMOS/LVTTL | 7 | 400 | 2 | 0.2 | very low | -40~125 | 323 | 5.9 | 154.7 | XSON8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74CBTLV3306DC | 74CBTLV3306DCH (935308824125) |
Active | b6 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74CBTLV3306GT | 74CBTLV3306GTX (935308825115) |
Active | b6 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74CBTLV3306DC | 74CBTLV3306DCH | 74CBTLV3306DC |
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| 74CBTLV3306GT | 74CBTLV3306GTX | 74CBTLV3306GT |
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文檔 (12)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74CBTLV3306 | 2-bit bus switch | Data sheet | 2024-06-24 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| cbtlv3306 | cbtlv3306 IBIS model | IBIS model | 2017-03-24 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
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