74LVC573A-Q100
Octal D-type transparent latch with 5 V tolerantinputs/outputs; 3-state
The 74LVC573A-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.2 to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
High-impedance when VCC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
參數(shù)類(lèi)型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC573ABQ-Q100 | 1.2?-?3.6 | TTL | ± 24 | 3.4 | 8 | low | -40~125 | 79 | 9.5 | 50 | DHVQFN20 |
| 74LVC573AD-Q100 | 1.2?-?3.6 | TTL | ± 24 | 3.4 | 8 | low | -40~125 | 85 | 27.6 | 61 | SO20 |
| 74LVC573APW-Q100 | 1.2?-?3.6 | TTL | ± 24 | 3.4 | 8 | low | -40~125 | 101 | 4.7 | 45 | TSSOP20 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC573ABQ-Q100 | 74LVC573ABQ‑Q100X (935300236115) |
Active | LVC573A |
DHVQFN20 (SOT764-1) |
SOT764-1 | SOT764-1_115 | |
| 74LVC573AD-Q100 | 74LVC573AD‑Q100J (935300237118) |
Active | 74LVC573AD |
SO20 (SOT163-1) |
SOT163-1 |
WAVE_BG-BD-1
|
SOT163-1_118 |
| 74LVC573APW-Q100 | 74LVC573APW‑Q100J (935300238118) |
Active | LVC573A |
TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT360-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC573ABQ-Q100 | 74LVC573ABQ‑Q100X | 74LVC573ABQ-Q100 |
|
|
| 74LVC573AD-Q100 | 74LVC573AD‑Q100J | 74LVC573AD-Q100 |
|
|
| 74LVC573APW-Q100 | 74LVC573APW‑Q100J | 74LVC573APW-Q100 |
|
|
文檔 (17)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| 74LVC573A_Q100 | Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state | Data sheet | 2020-03-30 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
| SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
| SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
| lvc573a | lvc573a IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN20_SOT764-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 2.5 mm x 4.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT764-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm body | Package information | 2022-06-21 |
| SOT163-1 | plastic, small outline package; 20 leads; 1.27 mm pitch; 12.8 mm x 7.5 mm x 2.65 mm body | Package information | 2024-11-15 |
| SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
| SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
| SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
| lvc573a | lvc573a IBIS model | IBIS model | 2013-04-09 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
Ordering, pricing & availability
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