74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge trigger
The 74AUP1G74?-?Q100 is a single positive edge triggered D?-?type flip?-?flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D?-?input that meets the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock transition will be stored in the flip?-?flop and appear at the Q output.
Schmitt?-?trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G74DC-Q100 | 0.8?-?3.6 | CMOS | ± 1.9 | 9.2 | 400 | ultra low | -40~125 | 203 | 34.1 | 113 | VSSOP8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1G74DC-Q100 | 74AUP1G74DC‑Q100H (935306605125) |
Active | p74 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1G74DC-Q100 | 74AUP1G74DC‑Q100H | 74AUP1G74DC-Q100 |
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文檔 (11)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP1G74_Q100 | Low-power D-type flip-flop with set and reset; positive?-?edge?trigger | Data sheet | 2024-08-09 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| aup1g74 | aup1g74 IBIS model | IBIS model | 2013-04-07 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
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