74AXP2T08-Q100
Dual supply, dual 2-input AND gate
The 74AXP2T08-Q100 is a dual supply, dual 2-input AND gate. It features four inputs (nA and nB), two outputs (nY) and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the outputs are referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCCI: 0.7 V to 2.75 V
VCCO: 1.2 V to 5.5 V
Low input capacitance; CI = 0.6 pF (typical)
Low output capacitance; CO = 1.8 pF (typical)
Low dynamic power consumption; CPD = 0.5 pF at VCCI = 1.2 V (typical)
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
Low static power consumption; ICCI = 0.5 μA (85 °C maximum)
Low static power consumption; ICCO = 1.8 μA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V; nA, nB inputs)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
JESD8-C (2.7 V to 3.6 V; nY outputs)
JESD12-6 (4.5 V to 5.5 V; nY outputs)
ESD protection:
MIL-STD-883, method 3015 Class 2. Exceeds 2 kV
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of VCCO
IOFF circuitry provides partial power-down mode operation
參數(shù)類型
| 型號 |
|---|
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AXP2T08DP-Q100 | 74AXP2T08DP‑Q100J (935334222118) |
Withdrawn / End-of-life |
TSSOP10 (SOT552-1) |
SOT552-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT552-1_118 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AXP2T08DP-Q100 | 74AXP2T08DP‑Q100J | 74AXP2T08DP‑Q100 |
|
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文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AXP2T08_Q100 | Dual supply, dual 2-input AND gate | Data sheet | 2019-03-29 |
| AN90029 | Pin FMEA for AXPnT family | Application note | 2021-07-13 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT552-1 | 3D model for products with SOT552-1 package | Design support | 2020-01-22 |
| axp2t08 | 74AXP2T08 IBIS model | IBIS model | 2016-03-02 |
| Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904 | AXP – Extremely low-power logic technology portfolio | Leaflet | 2019-04-05 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP10_SOT552_mk | plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT552-1 | plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2025-03-19 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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