74LVC2G02-Q100
Dual 2-input NOR gate
The 74LVC2G02-Q100 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G02DC-Q100 | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.4 | 150 | 2 | low | -40~125 | 200 | 32.4 | 110 | VSSOP8 |
| 74LVC2G02DP-Q100 | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.4 | 150 | 2 | low | -40~125 | 210 | 18.8 | 104 | TSSOP8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G02DC-Q100 | 74LVC2G02DC‑Q100H (935300458125) |
Active | V02 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC2G02DP-Q100 | 74LVC2G02DP‑Q100H (935300459125) |
Active | V02 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G02DC-Q100 | 74LVC2G02DC‑Q100H | 74LVC2G02DC-Q100 |
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| 74LVC2G02DP-Q100 | 74LVC2G02DP‑Q100H | 74LVC2G02DP-Q100 |
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文檔 (14)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G02_Q100 | Dual 2-input NOR gate | Data sheet | 2023-08-15 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| 001aah780 | Block diagram: 74LVC2G02DC, 74LVC2G02DP, 74LVC2G02GD, 74LVC2G02GM, 74LVC2G02GT | Block diagram | 2009-11-04 |
| mna716 | Block diagram: 74LVC2G02DC, 74LVC2G02DP, 74LVC2G02GD, 74LVC2G02GM, 74LVC2G02GT | Block diagram | 2009-11-04 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| lvc2g02 | 74LVC2G02 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
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