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可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVC2G86DC | 74LVC2G86DC,125 | 935278826125 | SOT765-1 | 訂單產(chǎn)品 |
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Click here for more information74LVC2G86DC
Dual 2-input EXCLUSIVE-OR gate
The 74LVC2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low-power dissipation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G86DC | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.3 | 150 | 2 | low | -40~125 | 200 | 32.4 | 110 | VSSOP8 |
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G86DC | 74LVC2G86DC,125 (935278826125) |
Active | V86 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 |
Boards
| Part number | Description | Type | Quick links | Shop link |
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描述 The NX-DP-GAN039-BSC double pulse evaluation board enables double-pulse testing of GaN FETs in a bottom-side cooled copper-clip package (CCPAK). It is optimized for low inductance and features a high-bandwidth current shunt that can be used to evaluate the switching performance with maximum precision. In addition, it can be used for thermal investigations and continuous operation of 3kW and beyond.
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類型 Evaluation board
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描述 The NX-DP-GAN039-TSC double pulse evaluation board enables double-pulse testing of GaN FETs in a top-side cooled copper-clip package (CCPAK). It is optimized for low inductance and features a high-bandwidth current shunt that can be used to evaluate the switching performance with maximum precision. In addition, it can be used for thermal investigations and continuous operation of 5kW and beyond.
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類型 Evaluation board
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描述 The NX-HB-GAN3R2-BSC half-bridge evaluation board provides the elements of a simple buck or boost converter. This enables the basic study of the switching characteristics and efficiency achievable with Nexperia’s 100V E-Mode GaN FETs. The circuit is configured for synchronous rectification, in either buck or boost mode. Selection jumpers allow the use of a single logic input or separate high / low level inputs. The voltage input and output can operate at up to 60 VDC, with a power output > 350 W
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類型 Evaluation board
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Series
文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G86 | Dual 2-input EXCLUSIVE-OR gate | Data sheet | 2024-04-26 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| lvc2g86 | 74LVC2G86 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT765-1_125 | VSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation | Packing information | 2025-10-24 |
| 74LVC2G86DC_Nexperia_Product_Reliability | 74LVC2G86DC Nexperia Product Reliability | Quality document | 2025-03-20 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC2G86DC | 74LVC2G86DC,125 | 935278826125 | Active | SOT765-1_125 | 3,000 |
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樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機構訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.