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Click here for more informationNPIC6C596D-Q100
Power logic 8-bit shift register; open-drain outputs
The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +125 °C
Low RDSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Enhanced cascading for multiple stages
All registers cleared with single input
Low power consumption
ESD protection:
HBM AEC-Q100-002 revision D exceeds 2500 V
CDM AEC-Q100-011 revision B exceeds 1000 V
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Applications
LED sign
Graphic status panel
Fault status indicator
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| NPIC6C596D‑Q100 | NPIC6C596D‑Q100,11 (935298529118) |
Obsolete | no package information | ||||
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| NPIC6C596D‑Q100 | NPIC6C596D‑Q100,11 | NPIC6C596D‑Q100 |
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Series
文檔 (5)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| NPIC6C596_Q100 | Power logic 8-bit shift register; open-drain outputs | Data sheet | 2020-06-22 |
| AN11537 | Pin FMEA for NPIC Family | Application note | 2019-10-07 |
| npic6c596 | NPIC6C596 IBIS model | IBIS model | 2016-05-30 |
| Nexperia_document_leaflet_Logic_NPIC_ShiftRegisters_201906 | NPIC Logic Shift Registers | Leaflet | 2019-07-12 |
| NPIC6C596D-Q100_Nexperia_Product_Reliability | NPIC6C596D-Q100 Nexperia Product Reliability | Quality document | 2024-06-16 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| npic6c596 | NPIC6C596 IBIS model | IBIS model | 2016-05-30 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.