74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374-Q100 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section.
The 74AVC16374-Q100 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.
Features and benefits
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Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from -40 °C to +85 °C
Wide supply voltage range from 1.2 V to 3.6 V
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Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
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ESD protection:
MIL-STD-883, method 3015 exceeds 1000 V
HBM JESD22-A114F exceeds 1000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
Low inductance multiple VCC and GND pins to minimize noise and ground bounce
Supports Live Insertion
Applications
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVC16374DGG-Q100 | 74AVC16374DGG‑Q10J (935301543118) |
Obsolete | no package information | ||||
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVC16374DGG-Q100 | 74AVC16374DGG‑Q10J | 74AVC16374DGG‑Q100 |
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文檔 (3)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AVC16374_Q100 | 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state | Data sheet | 2017-03-30 |
| AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
| avc16374 | 74AVC16374 IBIS model | IBIS model | 2019-01-09 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| avc16374 | 74AVC16374 IBIS model | IBIS model | 2019-01-09 |
Ordering, pricing & availability
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