74LVC1G38-Q100
2-input NAND gate; open drain
The 74LVC1G38-Q100 is a single 2-input NAND gate with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Open drain outputs
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G38GV-Q100 | 1.65?-?5.5 | CMOS/LVTTL | 32 | 2.3 | 175 | 1 | low | -40~125 | 270 | 63.3 | 169 | TSOP5 |
| 74LVC1G38GW-Q100 | 1.65?-?5.5 | CMOS/LVTTL | 32 | 2.3 | 175 | 1 | low | -40~125 | 311 | 80.9 | 181 | TSSOP5 |
| 74LVC1G38GZ-Q100 | 1.65?-?5.5 | CMOS/LVTTL | low | -40~125 | XSON5 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC1G38GV-Q100 | 74LVC1G38GV‑Q100H (935302104125) |
Active | YB |
TSOP5 (SOT753) |
SOT753 |
WAVE_BG-BD-1
|
SOT753_125 |
| 74LVC1G38GW-Q100 | 74LVC1G38GW‑Q100H (935302105125) |
Active | YB |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
| 74LVC1G38GZ-Q100 | 74LVC1G38GZ‑Q100YL (935691734315) |
Active | YB |
XSON5 (SOT8065-1) |
SOT8065-1 | SOT8065-1_315 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G38GV-Q100 | 74LVC1G38GV‑Q100H | 74LVC1G38GV-Q100 |
|
|
| 74LVC1G38GW-Q100 | 74LVC1G38GW‑Q100H | 74LVC1G38GW-Q100 |
|
|
| 74LVC1G38GZ-Q100 | 74LVC1G38GZ‑Q100YL | 74LVC1G38GZ-Q100 |
|
|
文檔 (16)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC1G38_Q100 | 2-input NAND gate; open drain | Data sheet | 2024-11-13 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT753 | 3D model for products with SOT753 package | Design support | 2019-01-22 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| lvc1g38 | 74LVC1G38 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| Leaflet_SOT8065_Minilogic | Leaflet_SOT8065 Minilogic | Leaflet | 2024-11-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT753 | plastic, surface-mounted package; 5 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Package information | 2022-05-31 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT8065-1 | Plastic thermal enhanced extremely thin small outline package withside-wettable flanks (SWF); no leads; 5 terminals; body 1.1 × 0.85 × 0.5mm | Package information | 2024-08-28 |
| MAR_SOT753 | MAR_SOT753 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。
模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT753 | 3D model for products with SOT753 package | Design support | 2019-01-22 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| lvc1g38 | 74LVC1G38 IBIS model | IBIS model | 2014-10-20 |
Ordering, pricing & availability
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