74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at different voltages for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals
Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced to VCC(A) and pins A, 2Y and 3Y are referenced to VCC(B).
The device ensures low static and dynamic power consumption and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the outputs, preventing any damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range:
VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V.
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 2A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 uA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C
Applications
參數(shù)類型
| 型號 |
|---|
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP2T1326GF | 74AUP2T1326GF,132 (935286883132) |
Obsolete | pf | no package information | |||
| 74AUP2T1326GF,115 (935286883115) |
Obsolete | pf | |||||
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP2T1326GF | 74AUP2T1326GF,132 | 74AUP2T1326GF |
|
|
| 74AUP2T1326GF | 74AUP2T1326GF,115 | 74AUP2T1326GF |
|
|
文檔 (5)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP2T1326 | low-power dual supply buffer/line driver; 3-state | Data sheet | 2017-05-03 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| 001aaj301 | Block diagram: 74AUP2T1326GF | Block diagram | 2009-11-03 |
| Nexperia_document_Logic_CombinationLogic_infocard_201710 | Combination logic solutions card | Leaflet | 2019-08-09 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
支持
如果您需要設計/技術支持，請告知我們并填寫 應答表 我們會盡快回復您。
模型
No documents available
Ordering, pricing & availability
樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機構訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。