74AVC1T45-Q100
Dual-supply voltage level translator/transceiver; 3-state
The 74AVC1T45-Q100 is a single bit, dual supply transceiver with 3-state output that enables bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
High noise immunity
CMOS low power dissipation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11( 0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
Maximum data rates:
500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (< 1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Dynamically controlled outputs
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號(hào) | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | Category |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AVC1T45GM-Q100 | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 1 | very low | -40~125 | 286 | 6.3 | 142 | XSON6 | Bi-directional | Direction controlled |
| 74AVC1T45GS-Q100 | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 1 | very low | -40~125 | 262 | 12.2 | 170 | XSON6 | Bi-directional | Direction controlled |
| 74AVC1T45GW-Q100 | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 1 | very low | -40~125 | 262 | 36.1 | 150 | TSSOP6 | Bi-directional | Direction controlled |
封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVC1T45GM-Q100 | 74AVC1T45GM‑Q100H (935299489125) |
Active | B5 |
XSON6 (SOT886) |
SOT886 | SOT886_125 | |
| 74AVC1T45GS-Q100 | 74AVC1T45GS‑Q100H (935690771125) |
Active | B5 |
XSON6 (SOT1202) |
SOT1202 | 暫無信息 | |
| 74AVC1T45GW-Q100 | 74AVC1T45GW‑Q100H (935299491125) |
Active | B5 |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVC1T45GM-Q100 | 74AVC1T45GM‑Q100H | 74AVC1T45GM-Q100 |
|
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| 74AVC1T45GS-Q100 | 74AVC1T45GS‑Q100H | 74AVC1T45GS-Q100 |
|
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| 74AVC1T45GW-Q100 | 74AVC1T45GW‑Q100H | 74AVC1T45GW-Q100 |
|
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文檔 (16)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AVC1T45_Q100 | Dual-supply voltage level translator/transceiver; 3-state | Data sheet | 2024-07-02 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT886 | 3D model for products with SOT886 package | Design support | 2019-10-03 |
| SOT1202 | 3D model for products with SOT1202 package | Design support | 2023-02-02 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| avc1t45 | 74AVC1T45 IBIS model | IBIS model | 2016-02-24 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DFN1410-6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| XSON6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| SOT886 | plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Package information | 2022-06-01 |
| SOT1202 | plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm body | Package information | 2022-06-01 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| MAR_SOT886 | MAR_SOT886 Topmark | Top marking | 2013-06-03 |
| MAR_SOT1202 | MAR_SOT1202 Topmark | Top marking | 2013-06-03 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT886 | 3D model for products with SOT886 package | Design support | 2019-10-03 |
| SOT1202 | 3D model for products with SOT1202 package | Design support | 2023-02-02 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| avc1t45 | 74AVC1T45 IBIS model | IBIS model | 2016-02-24 |
Ordering, pricing & availability
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