74ALVCH16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.
With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW?-?to?-?HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock.
When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Output drive capability 50 ? transmission lines at 85°C
All data inputs have bushold
Complies with JEDEC standard no. 8-1A
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16823DGG | 1.2?-?3.6 | TTL | ± 24 | 2.1 | 350 | low | -40~85 | 93 | 21 | TSSOP56 |
封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16823DGG | 74ALVCH16823DGG,11 (935259030118) |
Active | ALVCH16823 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16823DGG | 74ALVCH16823DGGS (935259030512) |
Withdrawn / End-of-life | ALVCH16823 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
暫無信息 |
| 74ALVCH16823DL | 74ALVCH16823DL,512 (935259020512) |
Obsolete | ALVCH16823 Standard Procedure Standard Procedure |
SSOP56 (SOT371-1) |
SOT371-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無信息 |
| 74ALVCH16823DL,518 (935259020518) |
Obsolete | ALVCH16823 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74ALVCH16823DL,112 (935259020112) |
Obsolete | ALVCH16823 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74ALVCH16823DL,118 (935259020118) |
Obsolete | ALVCH16823 Standard Procedure Standard Procedure | 暫無信息 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVCH16823DGG | 74ALVCH16823DGG,11 | 74ALVCH16823DGG |
|
|
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVCH16823DGG | 74ALVCH16823DGGS | 74ALVCH16823DGG |
|
|
| 74ALVCH16823DL | 74ALVCH16823DL,512 | 74ALVCH16823DL |
|
|
| 74ALVCH16823DL | 74ALVCH16823DL,518 | 74ALVCH16823DL |
|
|
| 74ALVCH16823DL | 74ALVCH16823DL,112 | 74ALVCH16823DL |
|
|
| 74ALVCH16823DL | 74ALVCH16823DL,118 | 74ALVCH16823DL |
|
文檔 (10)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVCH16823 | 18-bit bus-interface D-type flip-flop with reset and enable; 3-state | Data sheet | 2024-07-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| sh00016 | Block diagram: 74ABT16823ADGG, 74ABT16823ADL, 74ALVCH16823DGG, 74ALVCH16823DL, 74ALVT16823DGG, 74ALVT16823DL | Block diagram | 2009-11-04 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16823 | alvch16823 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| SOT371-1 | plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body | Package information | 2020-04-21 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。
模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16823 | alvch16823 IBIS model | IBIS model | 2013-04-08 |
Ordering, pricing & availability
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