74AVCH8T245
8-bit dual supply translating transceiver with configurable voltage translation; 3-state
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Maximum data rates:
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 2.5 V translation)
210 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | Category |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AVCH8T245BQ | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 8 | very low | -40~125 | 67 | 6.2 | 41 | DHVQFN24 | Bi-directional | Direction controlled |
| 74AVCH8T245PW | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 8 | very low | -40~125 | 81 | 2.3 | 36 | TSSOP24 | Bi-directional | Direction controlled |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVCH8T245BQ | 74AVCH8T245BQ,118 (935284592118) |
Active | VCH8T245 |
DHVQFN24 (SOT815-1) |
SOT815-1 | SOT815-1_118 | |
| 74AVCH8T245PW | 74AVCH8T245PW:118 (935284594118) |
Active | AVCH8T245 |
TSSOP24 (SOT355-1) |
SOT355-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT355-1_118 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVCH8T245BQ | 74AVCH8T245BQ,118 | 74AVCH8T245BQ |
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| 74AVCH8T245PW | 74AVCH8T245PW:118 | 74AVCH8T245PW |
|
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文檔 (11)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AVCH8T245 | 8-bit dual supply translating transceiver with configurable voltage translation; 3-state | Data sheet | 2024-07-02 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| SOT815-1 | 3D model for products with SOT815-1 package | Design support | 2019-10-03 |
| SOT355-1 | 3D model for products with SOT355-1 package | Design support | 2020-01-22 |
| avch8t245 | 74AVCH8T245 IBIS model | IBIS model | 2019-01-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN24_SOT815-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 24 terminals; 0.5 mm pitch; 3.5 mm x 5.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| SOT815-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 24 terminals; 0.5 mm pitch; 5.5 mm x 3.5 mm x 1 mm body | Package information | 2021-08-17 |
| SOT355-1 | plastic, thin shrink small outline package; 24 leads; 0.65 mm pitch; 7.8 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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