74LVC2G240
Dual inverting buffer/line driver; 3-state
The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G240DC | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 206 | 32.9 | 117 | VSSOP8 |
| 74LVC2G240DP | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 220 | 19.1 | 107 | TSSOP8 |
| 74LVC2G240GN | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 247 | 155 | XSON8 | |
| 74LVC2G240GS | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 284 | 152 | XSON8 | |
| 74LVC2G240GT | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 339 | 5.7 | 166 | XSON8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G240DC | 74LVC2G240DC,125 (935274508125) |
Active | V40 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC2G240DP | 74LVC2G240DP,125 (935272529125) |
Active | V240 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74LVC2G240GN | 74LVC2G240GN,115 (935292242115) |
Active | V2 |
XSON8 (SOT1116) |
SOT1116 | SOT1116_115 | |
| 74LVC2G240GS | 74LVC2G240GS,115 (935292797115) |
Active | V2 |
XSON8 (SOT1203) |
SOT1203 | SOT1203_115 | |
| 74LVC2G240GT | 74LVC2G240GT,115 (935282652115) |
Active | V40 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G240GF | 74LVC2G240GF,115 (935291505115) |
Obsolete | no package information | ||||
| 74LVC2G240GM | 74LVC2G240GM,125 (935282651125) |
Obsolete | V40 |
XQFN8 (SOT902-2) |
SOT902-2 | SOT902-2_125 | |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G240DC | 74LVC2G240DC,125 | 74LVC2G240DC |
|
|
| 74LVC2G240DP | 74LVC2G240DP,125 | 74LVC2G240DP |
|
|
| 74LVC2G240GN | 74LVC2G240GN,115 | 74LVC2G240GN |
|
|
| 74LVC2G240GS | 74LVC2G240GS,115 | 74LVC2G240GS |
|
|
| 74LVC2G240GT | 74LVC2G240GT,115 | 74LVC2G240GT |
|
|
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G240GF | 74LVC2G240GF,115 | 74LVC2G240GF |
|
|
| 74LVC2G240GM | 74LVC2G240GM,125 | 74LVC2G240GM |
|
|
文檔 (26)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G240 | Dual inverting buffer/line driver; 3-state | Data sheet | 2024-04-30 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mna958 | Block diagram: 74LVC2G240DC, 74LVC2G240DP, 74LVC2G240GM, 74LVC2G240GT | Block diagram | 2009-11-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| SOT1116 | 3D model for products with SOT1116 package | Design support | 2023-02-02 |
| SOT1203 | 3D model for products with SOT1203 package | Design support | 2023-02-02 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| lvc2g240 | 74LVC2G240 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| XQFN8_SOT902-2_mk | plastic, extremely thin quad flat package; 8 terminals; 0.55 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| XSON8_SOT1203_mk | plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body | Marcom graphics | 2019-02-04 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT902-2 | plastic, leadless extremely thin quad flat package; 8 terminals; 0.5 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Package information | 2020-04-21 |
| SOT1116 | plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm body | Package information | 2022-06-02 |
| SOT1203 | plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| MAR_SOT1116 | MAR_SOT1116 Topmark | Top marking | 2013-06-03 |
| MAR_SOT1203 | MAR_SOT1203 Topmark | Top marking | 2013-06-03 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| SOT1116 | 3D model for products with SOT1116 package | Design support | 2023-02-02 |
| SOT1203 | 3D model for products with SOT1203 package | Design support | 2023-02-02 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| lvc2g240 | 74LVC2G240 IBIS model | IBIS model | 2014-10-20 |
Ordering, pricing & availability
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