74AUP1T50
Low-power buffer with voltage-level translator
The 74AUP1T50 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.
The 74AUP1T50 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.
Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
Low static power consumption; ICC = 1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類(lèi)型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T50GW | 2.3?-?3.6 | CMOS | ± 4 | 70 | 1 | ultra low | -40~125 | 316 | 86 | 186 | TSSOP5 |
| 74AUP1T50GX | 2.3?-?3.6 | CMOS | ± 4 | 70 | 1 | ultra low | -40~125 | 340 | 105 | 206 | X2SON5 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1T50GW | 74AUP1T50GWH (935690083125) |
Active | 5E |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
| 74AUP1T50GX | 74AUP1T50GXH (935690084125) |
Active | 5E |
X2SON5 (SOT1226-3) |
SOT1226-3 | SOT1226-3_125 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1T50GW | 74AUP1T50GWH | 74AUP1T50GW |
|
|
| 74AUP1T50GX | 74AUP1T50GXH | 74AUP1T50GX |
|
|
文檔 (14)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| 74AUP1T50 | Low-power buffer with voltage-level translator | Data sheet | 2023-07-26 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT1226-3 | 3D model for products with SOT1226-3 package | Design support | 2021-01-28 |
| aup1t50 | IBIS model of 74AUP1T50 | IBIS model | 2017-12-18 |
| Nexperia_74AUP1Txx_voltage_translators | Single supply logic gates with voltage translation | Leaflet | 2018-06-18 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT1226-3 | plastic thermal enhanced extremely thin small outline package; no leads;5 terminals; body 0.8 x 0.8 x 0.32 mm | Package information | 2020-08-27 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
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