74AVC9112
1-to-4 fan-out buffer
The 74AVC9112 is a 1-to-4 fan-out buffer suitable for use in clock distribution. It has a data input (A), four data outputs (Yn) and an output enable input (OE). VCC can be supplied at any voltage between 0.8 V and 3.6 V. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range:
VCC: 0.8 V to 3.6 V
Inputs accept voltages up to 3.6 V
Maximum data rates:
380 Mbit/s (3.3 V)
200 Mbit/s (2.5 V)
200 Mbit/s (1.8 V)
150 Mbit/s (1.5 V)
100 Mbit/s (1.2 V)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AVC9112DC | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 190 | 1 | very low | -40~125 | 194 | 23.9 | 104 | VSSOP8 |
| 74AVC9112GT | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 190 | 1 | very low | -40~125 | 271 | 3.1 | 118 | XSON8 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVC9112DC | 74AVC9112DCH (935690124125) |
Active | Bb |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74AVC9112GT | 74AVC9112GTX (935690125115) |
Active | Bb |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVC9112DC | 74AVC9112DCH | 74AVC9112DC |
|
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| 74AVC9112GT | 74AVC9112GTX | 74AVC9112GT |
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文檔 (12)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AVC9112 | 1-to-4 fan-out buffer | Data sheet | 2024-07-08 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| avc9112 | 74AVC9112 IBIS model | IBIS model | 2018-06-18 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
支持
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