74HC3G34-Q100; 74HCT3G34-Q100
Triple buffer gate
The 74HC3G34-Q100; 74HCT3G34-Q100 is a triple buffer. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC3G34-Q100: CMOS level
For 74HCT3G34-Q100: TTL level
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC3G34DC-Q100 | 2.0?-?6.0 | CMOS | ± 5.2 | 36 | 3 | low | -40~125 | 205 | 35.4 | 115 | VSSOP8 |
| 74HC3G34DP-Q100 | 2.0?-?6.0 | CMOS | ± 5.2 | 36 | 3 | low | -40~125 | 217 | 20.7 | 106 | TSSOP8 |
| 74HCT3G34DC-Q100 | 4.5?-?5.5 | TTL | ± 4 | 36 | 3 | low | -40~125 | 205 | 35.4 | 115 | VSSOP8 |
| 74HCT3G34DP-Q100 | 4.5?-?5.5 | TTL | ± 4 | 36 | 3 | low | -40~125 | 217 | 20.7 | 106 | TSSOP8 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC3G34DC-Q100 | 74HC3G34DC‑Q100H (935300223125) |
Active | P34 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74HC3G34DP-Q100 | 74HC3G34DP‑Q100H (935300219125) |
Active | H34 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74HCT3G34DC-Q100 | 74HCT3G34DC‑Q100H (935300221125) |
Active | U34 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74HCT3G34DP-Q100 | 74HCT3G34DP‑Q100H (935300222125) |
Active | T34 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC3G34DC-Q100 | 74HC3G34DC‑Q100H | 74HC3G34DC-Q100 |
|
|
| 74HC3G34DP-Q100 | 74HC3G34DP‑Q100H | 74HC3G34DP-Q100 |
|
|
| 74HCT3G34DC-Q100 | 74HCT3G34DC‑Q100H | 74HCT3G34DC-Q100 |
|
|
| 74HCT3G34DP-Q100 | 74HCT3G34DP‑Q100H | 74HCT3G34DP-Q100 |
|
|
文檔 (11)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74HC_HCT3G34_Q100 | Triple buffer gate | Data sheet | 2024-01-02 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
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